VTERB-BLK-X2-UT4【PDF 7/34 页】LICENSE VITERBI DECODER XP2

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Chapter 2:

Functional Description

This chapter provides a functional description of the Block Viterbi Decoder IP core.

Figure 2-1 shows the interface diagram for Block Viterbi Decoder. The diagram shows all of the available ports for

the IP. It should be noted that not all the I/O ports are available for all configurations.

Figure 2-1. Block Viterbi Decoder Interface Diagram

din0

din1

din2

din3

din4

din5

din6

dout

outvalid

obvalid

ber

bervalid

clk

rstn

pbstart

Block

Viterbi Decoder

rfib

ibstart

ibend

ppset

inrate

outrate

pp0

pp1

General Description

Viterbi decoding is an efficient algorithm for decoding convolutionally encoded sequences corrupted by channel

noise back to the original sequence. A digital transmit-receive system shown in Figure 2-2 uses a Viterbi decoder

for decoding the convolutionally encoded data. The digital data stream (e.g., voice, image, or any packetized data)

is encoded, modulated, and transmitted through a wired or wireless channel. A “noise” block connected to the

channel symbolically denotes the channel noise. The data received from the channel at the receiver side is first

demodulated and then decoded using the Viterbi decoder. The decoded output is equivalent to the transmitted dig-

ital data stream.

Figure 2-2. Digital Transmit-Receive System

Transmitted

Data Stream

Convolutional

Encoder

Modulator

Channel

Demodulator

Block Viterbi

Decoder

Received

Data Stream

Noise

Convolutional Encoding

Figure 2-3 shows an example of convolutional encoding. In this example, each input symbol has two corresponding

output symbols; hence the encoding is called 1/2 rate convolutional encoding. To generate the output, the encoder

uses seven values of the input signal, one present and six past. The set of past values of input data is called the

“state” of the encoder. The number of input data values used to generate the code is called the constraint length

(K). In this case, the constraint length is 7. Each set of outputs is generated by XOR-ing a pattern of current and

shifted values of input data. The patterns used to generate the coded output value can be expressed as binary

strings called generator polynomials (GP). In this example, the generator polynomials are 171 and 133 (in octal).

IPUG32_02.7, June 2010

7

Block Viterbi Decoder User’s Guide

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相关PDF资料

VTERB-DECO-XP-N1 IP CORE VITERBI DECODER XPGA

VTP110F POLYSWITCH PTC RESET 1.1A STRAP

VTP175LF POLYSWITCH PTC RESET 1.75A STRAP

VTP210GF POLYSWITCH PTC RESET 2.1A STRAP

VTP210SF POLYSWITCH PTC RESET 2.1A STRAP

W51-A121B1-10 CIRCUIT BREAKER THERM 10A ILLUM

W54-XC2A4B10-40 CIRCUIT BREAKER THERMAL 40AMP

WV-089047-10-9 LABEL ID PRODUCTS

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